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Showing results 41 to 60 of 107 < previous next >

Issue Date	Title	Author(s)
2010	Image Compression Using Discrete Tchebichef Transform Algorithm	Senapati, R K; Pati, U C; Mahapatra, K K
2014	Implementation of Fuzzy-PID Controller to Liquid Level System using LabVIEW	Prusty, S B; Pati, U C; Mahapatra, K K
Jun-2015	Implementation of Input Data Buffering and Scheduling Methodology for 8 Parallel MDC FFT	Locharla, G R; Kumar K, S; Mahapatra, K K; Ari, S
Jun-2015	An Improved AES Hardware Trojan Benchmark to Validate Trojan Detection Schemes in an ASIC Design Flow	Kumar K, S; Chanamala, R; Sahoo, S R; Mahapatra, K K
Mar-2012	An Improved Feedthrough Logic for Low Power Circuit Design	Sahoo, S R; Mahapatra, K K
Feb-2012	An Improved Low Dynamic Power High Performance Adder	Sahoo, S R; Mahapatra, K K
Mar-2012	Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits	D, Srinivasa V S Sarma; Mahapatra, K K
Apr-2013	An Improved VLSI Architecture of S-box for AES Encryption	Kumar, S; Sharma, V K; Mahapatra, K K
Dec-2011	An Intelligent Control of Solid oxide Fuel cell voltage	Bhuyan, K C; Mahapatra, K K
Feb-2015	Investigation on Transient Response of Fuel Cell Power Conditioning Unit During Rapid Load Changes	Padhee, S; Pati, U C; Mahapatra, K K
2006	A Lossless Image Compression Technique using Simple Arithmetic Operations and its FPGA Implementation	Pattanaik, S K; Mahapatra, K K
Dec-2011	A Low Complexity Embedded Image Coding Algorithm Using Hierarchical Listless DTT	Senapati, R K; Pati, U C; Mahapatra, K K
Dec-2010	A Low Complexity Orthogonal 8×8 Transform Matrix for Fast Image Compression	Senapati, R K; Pati, U C; Mahapatra, K K
2010	Low Cost System on Chip Design for Audio Processing	Swain, Ayaskanta; Mahapatra, K K
Mar-2013	Low Latency VLSI Architecture of S-box for AES Encryption	Kumar, S; Sharma, V K; Mahapatra, K K
Oct-2011	A Low Power Circuit Technique for Feedthrough Logic	Sahoo, S R; Mahapatra, K K
2008	Low Power Filter Design using a Novel Dual Edge Triggered Latch	Das, J K; Mahapatra, K K
Jun-2011	A Low-Power Circuit Technique for Dynamic CMOS Logic	Meher, P; Mahapatra, K K
Oct-2014	A Low-Power CMOS Flip-Flop for High Performance Processors	Meher, P; Mahapatra, K K
Dec-2015	Modified Configurable RO PUF with Improved Security Metrics	Sahoo, S R; Kumar, S; Mahapatra, K K

Showing results 41 to 60 of 107 < previous next >