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|Title:||A Low-Power CMOS Flip-Flop for High Performance Processors|
Mahapatra, K K
|Citation:||TENCON-2014, Bangkok, Thailand, 22-25 October 2014.|
|Abstract:||A significant amount of the total power in highly synchronous systems gets dissipated over clock networks. Therefore, low-power clocking schemes would be promising approaches for high performance designs. To reduce the power consumption and delay, a new flip-flop circuit technique has been designed in CMOS domino logic. These flip-flops are a class of dynamic circuit that can be interfaced with both static and dynamic circuits. This flip-flop results in significant energy savings and operates in high speed. Based on simulation results of UMC 180 nm technology and 200 MHz frequency, we have simulated the flip-flop circuit and compared the result with the previous proposed flip-flops simulated with the same environment. The comparison results of the proposed flip-flop with the previous proposed flip-flop shows that the proposed circuit reduces 80% of power consumption and the speed increases to 70-90%.|
|Description:||Copyright belongs to proceeding publisher|
|Appears in Collections:||Conference Papers|
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