DSpace@nitr >
National Institue of Technology- Rourkela >
Conference Papers >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1668

Title: Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits
Authors: D, Srinivasa V S Sarma
Mahapatra, K K
Keywords: Domino logic
leakage current
noise tolerance
power consumption
Issue Date: Mar-2012
Citation: Students Conference on Engineering and Systems (SCES),16-18 March 2012, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh, India
Abstract: Dynamic CMOS gates are widely exploited in highperformance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the subthreshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is designed. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realize wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness.
Description: Copyright belongs to proceeding publisher
URI: http://hdl.handle.net/2080/1668
Appears in Collections:Conference Papers

Files in This Item:

File Description SizeFormat
Improved Techniques.pdf2895KbAdobe PDFView/Open

Show full item record

All items in DSpace are protected by copyright, with all rights reserved.

 

Powered by DSpace Feedback