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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1687

Title: An Improved Low Dynamic Power High Performance Adder
Authors: Sahoo, S R
Mahapatra, K K
Keywords: CMOS logic circuits
low-power
adder
Issue Date: Feb-2012
Citation: V-IMPACT-2012, 18-19 Feb, VIT Campus Jaipur, Rajasthan.
Abstract: This paper presents the design of a low power dynamic logic circuits using a new CMOS dynamic logic family called as low dynamic power dynamic logic i.e. LDPD. Dynamic logic styles are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic styles. The proposed circuit has very less dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the proposed modified low-power structure reduces the dynamic power approximately by 36% for 10-stage of inverters and 4-bit ripple carry adder. The concept is validated through extensive simulation. The limitation of dynamic logic styles like charge redistribution and requirement of inverter during cascading are completely eliminated.
Description: Copyright belongs to proceeding publisher
URI: http://hdl.handle.net/2080/1687
Appears in Collections:Conference Papers

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