Implementation of Input Data Buffering and Scheduling Methodology for 8 Parallel MDC FFT

Abstract

The MIMO-OFDM improves the link budget, simplifies the receiver and decreases the peak to average power ratio (PAPR) of a transmitting terminal. It includes multiple antennas for transmission and reception. The buffering and scheduling methodology of the data arrived from multiple antennas is very critical in reducing memory size and power consumption. This paper presents the Data Buffering, Scheduling methodology and their implementation for an eight parallel variable length Multipath Delay Commutator (MDC) FFT processor suitable for IEEE 802.11ac compliant MIMO-OFDM systems. It starts with a mathematical model for an 8 parallel variable length MDC FFT to understand the requirement of input buffer. Input buffer is required to park eight streams of the samples received serially at baseband processor and to schedule the ordered data onto eight channels such that the multimode FFT processing can be done efficiently and correctly. Proposed buffer can handle the data in four different orders for FFT core while operating in 512/256/128/64 point mode respectively. Proposed design consists of register banks, which can simplify the routing and save power. Also, this design is free from address conflict that may occur with SDRAM. The design is synthesized using TSMC 65nm library. The area and dynamic power results are presented for the implementation.