A Low Power Circuit Technique for Feedthrough Logic

Abstract

This paper presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough logic. The proposed circuit has very low dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The proposed circuit has been simulated at 0.18 µm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the dynamic power reduces approximately by 40% for 10-stage of inverters and 4-bit ripple carry adder in comparison to existing feedthrough logic. The problem of requirement of output inverter and non- inverting logic are also completely eliminated in the proposed design.