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Results 1-8 of 8 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
Oct-2011
A Low Power Circuit Technique for Feedthrough Logic
Sahoo, S R
;
Mahapatra, K K
Mar-2012
An Improved Feedthrough Logic for Low Power Circuit Design
Sahoo, S R
;
Mahapatra, K K
Mar-2012
Performance Analysis of Modified Feedthrough Logic for Low Power and High Speed
Sahoo, S R
;
Mahapatra, K K
Feb-2012
An Improved Low Dynamic Power High Performance Adder
Sahoo, S R
;
Mahapatra, K K
Jan-2015
On-Chip Comparison based Secure Output Response Compactor for Scan-based Attack Resistance
Sudeendra, K K
;
Lodha, K
;
Sahoo, S R
;
Mahapatra, K K
Jun-2015
A Novel ROPUF for Hardware Security
Sahoo, S R
;
Kumar, S
;
Mahapatra, K K
Jun-2015
An Improved AES Hardware Trojan Benchmark to Validate Trojan Detection Schemes in an ASIC Design Flow
Kumar K, S
;
Chanamala, R
;
Sahoo, S R
;
Mahapatra, K K
Dec-2015
Modified Configurable RO PUF with Improved Security Metrics
Sahoo, S R
;
Kumar, S
;
Mahapatra, K K
Discover
Author
2
Kumar, S
1
Chanamala, R
1
Kumar K, S
1
Lodha, K
1
Sudeendra, K K
Subject
3
Feedthrough logic (FTL)
2
adder
2
CMOS logic circuits
2
low-power
2
low-power adder
2
Security
1
AES
1
ASIC
1
ATE
1
Challenge Response Pair (CRP)
.
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Date issued
4
2015
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2012
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2011