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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1678

Title: Performance Analysis of Modified Feedthrough Logic for Low Power and High Speed
Authors: Sahoo, S R
Mahapatra, K K
Keywords: Feedthrough logic (FTL)
dynamic CMOS logic circuit
high performance
low-power adder
Issue Date: Mar-2012
Publisher: IEEE
Citation: : IEEE – International Conference on Advances in Engineering, Science And Management(Icaesm-2012), 30-31 March 2012, Tamilnadu.
Abstract: In this paper the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrogh logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and to further improve its speed we proposed another circuit which improves the speed by sacrificing dynamic power consumption. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the proposed modified low-power structure reduces the dynamic power approximately by 35% and the modified structure for high performance achieves a speed up- 1.3 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing feedthrough logic. The concept is validated through extensive simulation. The problem of requirement of...
Description: Copyright for this paper belongs to IEEE
URI: http://hdl.handle.net/2080/1678
Appears in Collections:Conference Papers

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