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Title: On-Chip Comparison based Secure Output Response Compactor for Scan-based Attack Resistance
Authors: Sudeendra, K K
Lodha, K
Sahoo, S R
Mahapatra, K K
Keywords: On-chip comparison
Scan-based attack
design for testability (DFT)
signature register
Side-channel attack
Issue Date: Jan-2015
Publisher: IEEE
Citation: IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA 2015), January 8-10, 2015
Abstract: Confidential Information transactions need cryptographic algorithms to give access to data only for authenticated individuals. In the era of smart phones and internet of things, most of the data exchange occurs between small and smart electronic gadgets. Cryptographic algorithms are necessary in smart gadgets to secure the sensitive data. Hardware implementations of cryptographic protocols on ASIC/FPGA devices are subject to various attacks from adversaries. In literature, we can find various attacks based on scan chain. The scan chains or Design for Testability (DFT) is included in the design to improve testability can become potential backdoors to conduct attacks. And also we can find several countermeasures to protect leaking of sensitive information in scan chains can be found in literature. One such technique is based on-chip comparison scheme. In this paper, we propose novel architecture for on-chip comparison circuit, which enhances the security and also reduces the test time of the circuit. The experimental result confirms the test time reduction.
Description: Copyright belongs to the Proceeding of Publisher
Appears in Collections:Conference Papers

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