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Issue Date	Title	Author(s)
Sep-2010	2-D Separable Discrete Hartley Transform Architecture for Efficient FPGA Resource	Sharma, V K; Agrawal, R; Pati, U C; Mahapatra, K K
Dec-2010	An Study of Removal of Subjective Redundancy in JPEG for Low Cost, Low Power, Computation efficient Circuit Design and High Compression Image	Sharma, V K; Pati, U C; Mahapatra, K K
Jan-2011	A Simple VLSI Architecture for Computation of 2-D DCT, Quantization and Zig-zag ordering for JPEG	Sharma, V K; Pati, U C; Mahapatra, K K
Feb-2011	An Efficient Distributed Arithmetic based VLSI Architecture for DCT	Sharma, V K; Mahapatra, K K; Pati, U C
Dec-2011	An ASIP for Image Enhancement Applications in Spatial Domain using LISA	Sarma, Anup; Sutar, Soubhagya; Sharma, V K; Mahapatra, K K
Mar-2012	A New Approach for High Performance and Efficient Design of CORDIC Processor	Jain, R K; Sharma, V K; Mahapatra, K K
Mar-2013	Low Latency VLSI Architecture of S-box for AES Encryption	Kumar, S; Sharma, V K; Mahapatra, K K
Apr-2013	An Improved VLSI Architecture of S-box for AES Encryption	Kumar, S; Sharma, V K; Mahapatra, K K
Apr-2014	Robust Facial Expression Recognition using Gabor Feature and Bayesian Discriminating Classifier	Piparsaniyan, Yamini; Sharma, V K; Mahapatra, K K