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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1709

Title: A New Approach for High Performance and Efficient Design of CORDIC Processor
Authors: Jain, R K
Sharma, V K
Mahapatra, K K
Keywords: Coordinate rotation digital computer (CORDIC)
vector rotation
FPGA
carry look ahead adder (CLA)
carry save adder (CSA)
Issue Date: Mar-2012
Publisher: IEEE
Citation: International Conference on recent advances in information technology (RAIT-2012) during 15-17 march 2012 At Indian School of Mines, Dhanbad
Abstract: This paper presents a new approach for the high performance and hardware efficient design of coordinate rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders (CLAs), exploiting one input as constant, in the angle adder/subtractor datapath speeds-up the computation while maintaining regularity. The proposed architecture is implemented in FPGA as well as in 180nm standard cell library. The proposed implementation has about 39% delay improvement in FPGA and about 34% delay improvement in standard cell technology as compared to basic structure. About 47% power savings has been achieved in the proposed structure.
Description: Copyright for this paper belongs to IEEE
URI: http://hdl.handle.net/2080/1709
Appears in Collections:Conference Papers

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