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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1295

Title: 2-D Separable Discrete Hartley Transform Architecture for Efficient FPGA Resource
Authors: Sharma, V K
Agrawal, R
Pati, U C
Mahapatra, K K
Keywords: Distributed Arithmetic
Discrete Hartley Transform
Discrete Cosine Transform
JPEG
Offset Binary Coding
Issue Date: Sep-2010
Publisher: IEEE
Citation: Int’l Conf. on Computer & Communication Technology, ICCCT’10 17-19 Sept. at MNNIT Allahabad
Abstract: Discrete cosine transform (DCT) is usually used in JPEG based image transform coding. This paper presents separable 2-D discrete Hartley transform (SDHT) and its Distributed Arithmetic (DA) based hardware architecture as an alternate to DCT in transform based coding of image compression. The proposed DA architecture for 1-D DHT has very less computations as compared to existing 1-D DCT. The proposed DHT architecture implemented in FPGA indicates a significant hardware savings as compared to FPGA resources used in an efficient memory based DA approach. The additional advantage of SDHT is that its inverse transform is same as forward transform with a constant division. This is demonstrated through a Xilinx FPGA XC2VP30 device.
Description: Copyright belongs to the Proceeding of Publisher
URI: http://hdl.handle.net/2080/1295
Appears in Collections:Conference Papers

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