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Results 1-10 of 15 (Search time: 0.003 seconds).
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Issue Date
Title
Author(s)
Jan-2015
On-Chip Comparison based Secure Output Response Compactor for Scan-based Attack Resistance
Sudeendra, K K
;
Lodha, K
;
Sahoo, S R
;
Mahapatra, K K
Jan-2015
A Novel On-Chip Self-Testing Signature Register for Low Cost Manufacturing Test
Lodha, K R
;
Kumar, S
;
Mahapatra, K K
Feb-2015
A Novel Fuzzy based Adaptive Control of the Four Tank System
Prusty, S B
;
Pati, U C
;
Mahapatra, K K
Feb-2015
Design and Simulation of a Modified Sliding Mode Controller Evaluated with a Conventional P&O MPPT Controller for Solar Applications
Kolluru, V R
;
Sahu, G
;
Mahapatra, K K
;
Subudhi, B
Feb-2015
Investigation on Transient Response of Fuel Cell Power Conditioning Unit During Rapid Load Changes
Padhee, S
;
Pati, U C
;
Mahapatra, K K
Feb-2015
Rapid Prototyping of FPGA Based Digital Controller of DSTATCOM for Load Compensation Under Distorted Utility Condition
Sahu, G
;
Kolluru, V R
;
Mahapatra, K K
Jun-2015
A Novel ROPUF for Hardware Security
Sahoo, S R
;
Kumar, S
;
Mahapatra, K K
Jun-2015
An Improved AES Hardware Trojan Benchmark to Validate Trojan Detection Schemes in an ASIC Design Flow
Kumar K, S
;
Chanamala, R
;
Sahoo, S R
;
Mahapatra, K K
Jun-2015
Implementation of Input Data Buffering and Scheduling Methodology for 8 Parallel MDC FFT
Locharla, G R
;
Kumar K, S
;
Mahapatra, K K
;
Ari, S
Aug-2015
Hardware Trojans: A State of the Art
Sudeendra Kumar, K
;
Mahapatra, K K
Discover
Author
4
Kumar, S
4
Sahoo, S R
2
Kolluru, V R
2
Kumar K, S
2
Pati, U C
2
Sahu, G
2
Sudeendra Kumar, K
1
Acharya, D P
1
Ari, S
1
Bhuyan, K C
.
next >
Subject
2
AES
2
design for testability (DFT)
2
Security
2
signature register
1
Anti-lock
1
ASIC
1
ATE
1
ATE memory
1
Benchmark
1
buck-boost
.
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