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Title: A Novel On-Chip Self-Testing Signature Register for Low Cost Manufacturing Test
Authors: Lodha, K R
Kumar, S
Mahapatra, K K
Keywords: ATE memory
design for testability (DFT)
signature register
test cost
test time
tester channel reduction
Issue Date: Jan-2015
Publisher: IEEE
Citation: IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA 2015), January 8-10, 2015
Abstract: Functional complexity, circuit density and performance of integrated circuits (ICs) are persistently escalating. Test data generated for such ICs, using de facto scan test, is expanding beyond gigabits. Precise comparison of such bulky data on automatic test equipment (ATE) demands huge memory, large number of scan channels, multiple drive and compare edges per tester cycle and augmented test time, that are collectively increasing test cost. In this paper an on-chip self-testing signature register is proposed which compact the test response and compares generated test signature with golden one, generating two bits of PASS/FAIL test result on single pin. This significantly reduces memory and scan channel requirement on ATE. Furthermore for 50% increase in scan chains, 32.70% reduction in test time is observed with little area overhead of 4.25% on scan design. The proposed architecture has also been validated through FPGA implementation.
Description: Copyright belongs to the Proceeding of Publisher
Appears in Collections:Conference Papers

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