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Issue DateTitleAuthor(s)
Mar-2013Low Latency VLSI Architecture of S-box for AES EncryptionKumar, S; Sharma, V K; Mahapatra, K K
Apr-2013An Improved VLSI Architecture of S-box for AES EncryptionKumar, S; Sharma, V K; Mahapatra, K K
Jan-2015A Novel On-Chip Self-Testing Signature Register for Low Cost Manufacturing TestLodha, K R; Kumar, S; Mahapatra, K K
Jun-2015A Novel ROPUF for Hardware SecuritySahoo, S R; Kumar, S; Mahapatra, K K
Nov-2015A Novel Regenerative and Anti-Lock Braking technique for Electric VehiclesMaliye, S; Kumar, S; Swain, A; Mahapatra, K K
Dec-2015Modified Configurable RO PUF with Improved Security MetricsSahoo, S R; Kumar, S; Mahapatra, K K

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