Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1668

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DC Field	Value	Language
dc.contributor.author	D, Srinivasa V S Sarma	-
dc.contributor.author	Mahapatra, K K	-
dc.date.accessioned	2012-04-04T12:05:55Z	-
dc.date.available	2012-04-04T12:05:55Z	-
dc.date.issued	2012-03	-
dc.identifier.citation	Students Conference on Engineering and Systems (SCES),16-18 March 2012, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh, India	en
dc.identifier.uri	http://hdl.handle.net/2080/1668	-
dc.description	Copyright belongs to proceeding publisher	en
dc.description.abstract	Dynamic CMOS gates are widely exploited in highperformance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the subthreshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is designed. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realize wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness.	en
dc.format.extent	2965159 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.subject	Domino logic	en
dc.subject	leakage current	en
dc.subject	noise tolerance	en
dc.subject	power consumption	en
dc.title	Improved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuits	en
dc.type	Article	en
Appears in Collections:	Conference Papers

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