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dc.contributor.authorD, Srinivasa V S Sarma-
dc.contributor.authorMahapatra, K K-
dc.identifier.citationStudents Conference on Engineering and Systems (SCES),16-18 March 2012, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh, Indiaen
dc.descriptionCopyright belongs to proceeding publisheren
dc.description.abstractDynamic CMOS gates are widely exploited in highperformance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the subthreshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is designed. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realize wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness.en
dc.format.extent2965159 bytes-
dc.subjectDomino logicen
dc.subjectleakage currenten
dc.subjectnoise toleranceen
dc.subjectpower consumptionen
dc.titleImproved Techniques for High Performance Noise-Tolerant Domino CMOS Logic Circuitsen
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