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http://hdl.handle.net/2080/1430
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| Title: | An Accurate Estimation of Power using Verilog |
| Authors: | Guntupalli, R
Mahapatra, K K |
| Keywords: | Leakage power,
Dynamic power,
power dissipation,
Bench mark,
Verilog |
| Issue Date: | 2011 |
| Citation: | International Conference on Electronics, Information and Communication Systems Engineering, ICEICE-2010, March, 28-30th 2011, Rajasthan |
| Abstract: | Power has become major design concern for complex
VLSI circuits today. Designer needs tool(s) that accurately estimate the power dissipation for a given design. We need two categories of tools that are useful for this purpose. One is power
optimization tools and, second is an analysis tool for estimating the power consumption in an existing netlist. This approach addresses the second issue by employing a VERILOG-based
approach for analysis of power consumption in CMOS logic designs. The design under test will either the result of logic synthesis with various optimization constraints or hand design done through schematic capture. The proposed approach used to analyse various benchmark circuits for power consumption, such as ISCAS bench mark circuits. The presented approach in this
paper consists of three phases: (1) Designing smart VERILOG simulation models, (2) Measuring transition activity at each node of the netlist and then estimate the power based on this activity
and on fan o... |
| URI: | http://hdl.handle.net/2080/1430 |
| Appears in Collections: | Conference Papers
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| ramesh_nitr.pdf | | 76Kb | Adobe PDF | View/Open |
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