DSpace@nitr >
National Institue of Technology- Rourkela >
Conference Papers >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1385

Title: Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition
Authors: Rout, P K
Panda, B P
Acharya, D P
Panda, G
Keywords: Phase frequency detector (PFD),
loop filter,
voltage controlled oscillator (VCO),
phase-locked loops (PLLs).
Issue Date: 2011
Citation: International Conference on Electronic Systems (ICES-2011), National Institute of Technology, Rourkela, 7-9th January, 2011
Abstract: Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The PLL is designed in GPDK090 library of CMOS 90nm process to operate at a frequency of 1GHz with a lock time of 280.6ns. This PLL circuit is observed to consume a power of 11.9mW from a 1.8-V DC supply.
URI: http://hdl.handle.net/2080/1385
Appears in Collections:Conference Papers

Files in This Item:

File Description SizeFormat
Analysis_and_Design_of_a_1GHz_PLL.pdf458KbAdobe PDFView/Open

Show full item record

All items in DSpace are protected by copyright, with all rights reserved.

 

Powered by DSpace Feedback