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dc.contributor.authorRout, P K-
dc.contributor.authorPanda, B P-
dc.contributor.authorAcharya, D P-
dc.contributor.authorPanda, G-
dc.identifier.citationInternational Conference on Electronic Systems (ICES-2011), National Institute of Technology, Rourkela, 7-9th January, 2011en
dc.description.abstractPhase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The PLL is designed in GPDK090 library of CMOS 90nm process to operate at a frequency of 1GHz with a lock time of 280.6ns. This PLL circuit is observed to consume a power of 11.9mW from a 1.8-V DC supply.en
dc.format.extent469966 bytes-
dc.subjectPhase frequency detector (PFD),en
dc.subjectloop filter,en
dc.subjectvoltage controlled oscillator (VCO),en
dc.subjectphase-locked loops (PLLs).en
dc.titleAnalysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisitionen
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