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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/823

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contributor.authorDas, J K-
contributor.authorMahapatra, K K-
date.accessioned2009-05-18T06:00:57Z-
date.available2009-05-18T06:00:57Z-
date.issued2008-
identifier.citationInternational Conference on Electronic Design, ICED, Penang December 1-3,2008.en
identifier.urihttp://dx.doi.org/10.1109/ICED.2008.4786698-
identifier.urihttp://hdl.handle.net/2080/823-
description.abstractIn the present investigation, a low power FIR filter using FDF structure is designed which is a key component in a hearing aid application. The details of design are presented. A novel low power latch using 10 transistors is pro-posed that uses dual edge triggering. It is shown a power saving up to 65% is achieved in the FIR filter using the proposed latch. This filter will find application in a hearing aid, which demands area/power constraint and would be useful for other DSP based portable devices.en
format.extent981651 bytes-
format.mimetypeapplication/pdf-
language.isoen-
publisherIEEEen
subjectFIR filtersen
subjectflip-flopsen
subjecthearing aidsen
subjectlow-power electronicsen
titleLow Power Filter Design using a Novel Dual Edge Triggered Latchen
typeArticleen
Appears in Collections:Conference Papers

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