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http://hdl.handle.net/2080/5675| Title: | A Robust Design Methodology for Fault-Tolerant FPGA Architecture |
| Authors: | Desai, Megh Mukherjee, Atin |
| Keywords: | Fault Tolerance FPGA Architecture Single Event Upset (SEU) Single Event Transient (SET) Dynamic Reconfiguration |
| Issue Date: | Dec-2025 |
| Citation: | 2nd IEEE International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM), IIT(ISM), Dhanbad, 20-22 December 2025 |
| Abstract: | As very large scale integration (VLSI) technology evolves, greater complexity, smaller transistor sizes, and higher densities of integration have rendered circuits more vulnerable to faults resulting from manufacturing defects, aging, environmental influences, and radiation. Fault tolerance in VLSI involves the capability of a system to ensure correct operation despite the occurrence of faults or failures. This ability is essential in applications where high reliability is needed, including aerospace, medical equipment, and safety-critical computing systems. Field programmable gate arrays (FPGAs) have become a major technology for the realization of fault-tolerant systems due to their reconfiguration, parallelism, and flexibility. This paper discusses some of the techniques for realizing fault-tolerant FPGAs and why they play a significant role in ensuring fault tolerant operation under failure conditions. |
| Description: | Copyright belongs to the proceeding publisher. |
| URI: | http://hdl.handle.net/2080/5675 |
| Appears in Collections: | Conference Papers |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 2025_ELEXCOM_MDesai_A Robust.pdf | 898.23 kB | Adobe PDF | View/Open Request a copy |
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