Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/5675
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dc.contributor.authorDesai, Megh-
dc.contributor.authorMukherjee, Atin-
dc.date.accessioned2026-02-11T05:37:01Z-
dc.date.available2026-02-11T05:37:01Z-
dc.date.issued2025-12-
dc.identifier.citation2nd IEEE International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM), IIT(ISM), Dhanbad, 20-22 December 2025en_US
dc.identifier.urihttp://hdl.handle.net/2080/5675-
dc.descriptionCopyright belongs to the proceeding publisher.en_US
dc.description.abstractAs very large scale integration (VLSI) technology evolves, greater complexity, smaller transistor sizes, and higher densities of integration have rendered circuits more vulnerable to faults resulting from manufacturing defects, aging, environmental influences, and radiation. Fault tolerance in VLSI involves the capability of a system to ensure correct operation despite the occurrence of faults or failures. This ability is essential in applications where high reliability is needed, including aerospace, medical equipment, and safety-critical computing systems. Field programmable gate arrays (FPGAs) have become a major technology for the realization of fault-tolerant systems due to their reconfiguration, parallelism, and flexibility. This paper discusses some of the techniques for realizing fault-tolerant FPGAs and why they play a significant role in ensuring fault tolerant operation under failure conditions.en_US
dc.subjectFault Toleranceen_US
dc.subjectFPGA Architectureen_US
dc.subjectSingle Event Upset (SEU)en_US
dc.subjectSingle Event Transient (SET)en_US
dc.subjectDynamic Reconfigurationen_US
dc.titleA Robust Design Methodology for Fault-Tolerant FPGA Architectureen_US
dc.typeArticleen_US
Appears in Collections:Conference Papers

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