Hardware Architecture Design for Area Constrained IntegralImage Generation for Face Detection Application

Abstract

Human face detection finds an important role in various Human-Computer Interaction (HCI) and computer vision applications. The seminal work of Viola Jones for automatic face detection found it's popularity in many such applications. The inherent parallelism in the algorithm makes it more applicable for hardware implementation. Itutilizes integral image computation as a preprocessing step to reduce the overall computation burden of Haar-like features. Although the calculation of the integral image consists of simple addition operations, the total number of operations increases with increase in image resolution. Therefore, for resource-constrained real-time embedded applications, the computation and storage of integral values present several design challenges. This paper proposes an optimized hardware architecture of integral image computation for a resource constraint low-cost system. The proposed architecture utilizes the advantage of overlapping area in the sliding window used to find face features in the Viola-Jones face detector. The architecture is simulated using VIVADO®Design Suite 2018.2 for the ZYNQ (ZC702)board. It is found that the implemented architecture achieve sasignificant reduction in the hardware resource utilization compared to the state-of-the-art integral image computation implementations