Reduced Latency Square-Root calculation for Signal Processing using Radix-4 Hyperbolic CORDIC

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2719

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DC Field	Value	Language
dc.contributor.author	Kumari, Aishwarya	-
dc.contributor.author	Acharya, D P	-
dc.date.accessioned	2017-06-07T10:34:07Z	-
dc.date.available	2017-06-07T10:34:07Z	-
dc.date.issued	2017-06	-
dc.identifier.citation	5th International Conference on Advanced Computing, Networking, and Informatics(ICACNI), NIT Goa, Goa, India, 1-3 June 2017	en_US
dc.identifier.uri	http://hdl.handle.net/2080/2719	-
dc.description	Copyright for this paper belongs to proceeding publisher	en_US
dc.description.abstract	Till now the CORDIC algorithm is primarily used to calculate only trigonometric operations. In the proposed work, we extend the Radix-4 CORDIC algorithm to the hyperbolic vectoring mode to implement fast computation of Square-Root. This paper illustrates the implementation of a regular VLSI architecture for Radix-4 hyperbolic vectoring CORDIC on FPGA platform. The speed can further be increased with higher version of FPGA devices. A comparison between Radix-2 and Radix-4 CORDIC algorithm based on the simulation results is also presented in the work.	en_US
dc.publisher	Springer	en_US
dc.subject	CORDIC algorithm	en_US
dc.subject	Radix-4	en_US
dc.subject	Pipelined architectures	en_US
dc.title	Reduced Latency Square-Root calculation for Signal Processing using Radix-4 Hyperbolic CORDIC	en_US
dc.type	Article	en_US
Appears in Collections:	Conference Papers

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