Please use this identifier to cite or link to this item:
Title: FPGA Prototyping and Parameterised based Resource Evaluation of Network on Chip Architecture
Authors: Swain, A K
Rajesh Kumar, B
Satpathy, S N
Mahapatra, K K
Keywords: NoC
Parametric Evaluation
Issue Date: Aug-2016
Publisher: IEEE
Citation: IEEE International Conference on Distributed Computing,VLSI,Electrical Circuits and Robotics(DISCOVER 2016), NIT Surathkal, India, 13-14 August 2016
Abstract: This paper investigates the various aspects of network on Chip(NoC) design and its FPGA implementation. A parametric approach of evaluating the FPGA resources, delay and maximum frequency of operation for a NoC design has been described which may help the designer to take early decision related to NoC designing and prototyping. Virtual channel(VC), flit buffer depth and flit data width are taken as the parameter for evaluation. The functional simulation results show a successful data transfer between different nodes of a 3x3 NoC. Increase in VCs increases the FPGA resources, delay and reduces the frequency of operation. The maximum frequency of operation is also affected by the variation of Flit Data Width and Flit Buffer Depth.
Description: Copyright belongs to the proceeding publisher
Appears in Collections:Conference Papers

Files in This Item:
File Description SizeFormat 
2016_DISCOVER_201_Ayas.pdf734.7 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.