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Title: A Novel PUF based SST to Prevent Distribution of Rejected ICs from Untrusted Assembly
Authors: Sudeendra Kumar, K
Hanumanta Rao, G
Sahoo, S
Mahapatra, K K
Keywords: Counterfeiting
Secure split test
Hardware metering.
Issue Date: Dec-2015
Publisher: IEEE
Citation: IEEE International Symposium on Nanoelectronic and Information Systems(IEEE-INIS-2015), Indore, India, 21-23 Dec 2015
Abstract: Globalization of semiconductor design, manufacturing, packaging and testing has led to several security issues like over production of chips, shipping of faulty or partially functional chips, intellectual property infringement, cloning, counterfeit chips and insertion of hardware trojans in design house or at foundry etc. Adversaries will extract chips from obsolete PCB’s and release used parts as new chips into the supply chain. The faulty chips or partially functioning chips can enter supply chain from untrusted Assembly Packaging and Test (APT) centers. These counterfeit parts are not reliable and cause catastrophic consequences in critical applications. To mitigate the counterfeits entering supply chain, to protect the Intellectual Property (IP) rights of owners and to meter the chip, Secure Split Test (SST) is a promising solution. CSST (Connecticut SST) is an improvement to SST, which simplifies the communication required between ATP center and design house. CSST addresses the scan tests, but it does not address the functional testing of chips. The functional testing of chips during production testing is critical in weeding out faulty chips in recent times. In this paper, we present a method called PUF-SST (Physical Unclonable Function –SST) to perform both scan tests and functional tests without compromising on security features described in CSST.
Description: Copyright belongs to proceeding publisher
Appears in Collections:Conference Papers

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