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http://hdl.handle.net/2080/2133| Title: | Design of High Speed Sense Amplifier for SRAM |
| Authors: | Chandankhede, R D Acharya, D P Patra, P K |
| Keywords: | Sense Amplifier SRAM architecture current controlled SA Cache memory |
| Issue Date: | 2014 |
| Publisher: | IEEE |
| Citation: | IEEE International Conference on Advanced Communication Control and Computing Technologies - ICACCCT May 8-10, 2014.Ramanathapuram, Tamilnadu, India. |
| Abstract: | 1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz |
| Description: | Copyright belongs to the Proceeding of Publisher |
| URI: | http://hdl.handle.net/2080/2133 |
| Appears in Collections: | Conference Papers |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IEEE- sense amplifier.pdf | 731.92 kB | Adobe PDF | View/Open |
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