Design of High Speed Sense Amplifier for SRAM

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2133

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DC Field	Value	Language
dc.contributor.author	Chandankhede, R D	-
dc.contributor.author	Acharya, D P	-
dc.contributor.author	Patra, P K	-
dc.date.accessioned	2014-05-28T10:51:36Z	-
dc.date.available	2014-05-28T10:51:36Z	-
dc.date.issued	2014	-
dc.identifier.citation	IEEE International Conference on Advanced Communication Control and Computing Technologies - ICACCCT May 8-10, 2014.Ramanathapuram, Tamilnadu, India.	en
dc.identifier.uri	http://hdl.handle.net/2080/2133	-
dc.description	Copyright belongs to the Proceeding of Publisher	en
dc.description.abstract	1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz	en
dc.format.extent	749490 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.subject	Sense Amplifier	en
dc.subject	SRAM architecture	en
dc.subject	current controlled SA	en
dc.subject	Cache memory	en
dc.title	Design of High Speed Sense Amplifier for SRAM	en
dc.type	Article	en
Appears in Collections:	Conference Papers

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