DSpace@nitr >
National Institue of Technology- Rourkela >
Conference Papers >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1687

Full metadata record

DC FieldValueLanguage
contributor.authorSahoo, S R-
contributor.authorMahapatra, K K-
date.accessioned2012-05-02T05:39:08Z-
date.available2012-05-02T05:39:08Z-
date.issued2012-02-
identifier.citationV-IMPACT-2012, 18-19 Feb, VIT Campus Jaipur, Rajasthan.en
identifier.urihttp://hdl.handle.net/2080/1687-
descriptionCopyright belongs to proceeding publisheren
description.abstractThis paper presents the design of a low power dynamic logic circuits using a new CMOS dynamic logic family called as low dynamic power dynamic logic i.e. LDPD. Dynamic logic styles are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic styles. The proposed circuit has very less dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the proposed modified low-power structure reduces the dynamic power approximately by 36% for 10-stage of inverters and 4-bit ripple carry adder. The concept is validated through extensive simulation. The limitation of dynamic logic styles like charge redistribution and requirement of inverter during cascading are completely eliminated.en
format.extent236366 bytes-
format.mimetypeapplication/pdf-
language.isoen-
subjectCMOS logic circuitsen
subjectlow-poweren
subjectadderen
titleAn Improved Low Dynamic Power High Performance Adderen
typeArticleen
Appears in Collections:Conference Papers

Files in This Item:

File Description SizeFormat
V-IMPACT-2012.pdf230KbAdobe PDFView/Open

Show simple item record

All items in DSpace are protected by copyright, with all rights reserved.

 

Powered by DSpace Feedback