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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1619

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contributor.authorSahoo, S R-
contributor.authorMahapatra, K K-
identifier.citationNational conference on VLSI Design and Embedded systems(NCVDES-2011) ,12-14 October 2011,CEERI,Pilani-333031(Rajasthan)en
descriptionCopyright belongs to proceeding publisheren
description.abstractThis paper presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough logic. The proposed circuit has very low dynamic power consumption compared to the recently proposed circuit techniques for the dynamic logic styles. The proposed circuit has been simulated at 0.18 ┬Ám, 1.8 V CMOS process technology. Intensive simulation results in Cadence environment shows that the dynamic power reduces approximately by 40% for 10-stage of inverters and 4-bit ripple carry adder in comparison to existing feedthrough logic. The problem of requirement of output inverter and non- inverting logic are also completely eliminated in the proposed design.en
format.extent116984 bytes-
subjectCMOS logic circuitsen
subjectfeedthrough logic (FTL)en
titleA Low Power Circuit Technique for Feedthrough Logicen
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