An ASIP for Image Enhancement Applications in Spatial Domain using LISA

Abstract

Application-specific instruction-set processor (ASIP) has programming flexibility and performance as compared to application specific integrated circuits (ASICs). This makes it attractive choice for the future embedded processor on systemon-chip (SOC) design. We have designed an ASIP using language for instruction-set architecture (LISA). The designed processor has optimized instructions (a total of 8) for the image enhancement applications in spatial domain. The processor architecture is tested by writing soft codes for four different image enhancement algorithms. Good qualities of enhanced images have been obtained by the simulations. Finally, the processor architecture is prototyped in FPGA and implemented using TSMC 0.18 μm CMOS standard cell technology library. The architecture uses 21.72 K gate counts and consumes total power of 2.489 mW at 50MHz clock frequency and supply voltage of 1.8 V.