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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2080/1559
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| Title: | A Survey on Hardware Implementation of IDEA Cryptosystem |
| Authors: | Mukherjee, S
Sahoo, Bibhudatta |
| Keywords: | FPGA
ASIC
IDEA
Block Cipher
Throughput
Multiplication modulo (2n + 1) |
| Issue Date: | 2011 |
| Publisher: | Taylor & Francis |
| Citation: | Information Security Journal: A Global Perspective, Volume 20, Issue 4-5, 2011 |
| Abstract: | The main goal of hardware implementation of a
cryptosystem is to make it compatible for high speed networks. The cryptographic algorithms are very much computationally intensive and to achieve a high speed execution, hardware is
necessary. In this paper, various hardware implementations of the IDEA cipher is discussed. The hardware implementation involves both ASIC and FPGA implementations and IDEA has been
implemented quite a several times in hardware. But a complete survey of all the previous implementations has not been presented
before. In each of these implementations, the focus has been made on the data throughput, area requirements and the architecture of the algorithm proposed. |
| Description: | Copyright for the paper belongs to Taylor & Francis |
| URI: | http://dx.doi.org/10.1080/19393555.2011.599098
http://hdl.handle.net/2080/1559 |
| Appears in Collections: | Journal Articles
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Files in This Item:
| File |
Description |
Size | Format |
|---|
| A Survey on Hardware.pdf | | 159Kb | Adobe PDF | View/Open |
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