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dc.contributor.authorMukherjee, S-
dc.contributor.authorSahoo, Bibhudatta-
dc.identifier.citationInformation Security Journal: A Global Perspective, Volume 20, Issue 4-5, 2011en
dc.descriptionCopyright for the paper belongs to Taylor & Francisen
dc.description.abstractThe main goal of hardware implementation of a cryptosystem is to make it compatible for high speed networks. The cryptographic algorithms are very much computationally intensive and to achieve a high speed execution, hardware is necessary. In this paper, various hardware implementations of the IDEA cipher is discussed. The hardware implementation involves both ASIC and FPGA implementations and IDEA has been implemented quite a several times in hardware. But a complete survey of all the previous implementations has not been presented before. In each of these implementations, the focus has been made on the data throughput, area requirements and the architecture of the algorithm proposed.en
dc.format.extent163065 bytes-
dc.publisherTaylor & Francisen
dc.subjectBlock Cipheren
dc.subjectMultiplication modulo (2n + 1)en
dc.titleA Survey on Hardware Implementation of IDEA Cryptosystemen
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