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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1519

Title: A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic
Authors: Meher, P
Mahapatra, K K
Keywords: Dynamic logic
domino logic
Delay
diode-footed domino
noise tolerance
power consumption
robustness
technology scaling
semi-dynamic logic
Issue Date: Jun-2011
Citation: International Conference on Computer Science and informatics, June 19-20, 2011, Bhubaneswar
Abstract: Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.
Description: Copyright belongs to proceeding publishers
URI: http://hdl.handle.net/2080/1519
Appears in Collections:Conference Papers

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