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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1519

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contributor.authorMeher, P-
contributor.authorMahapatra, K K-
identifier.citationInternational Conference on Computer Science and informatics, June 19-20, 2011, Bhubaneswaren
descriptionCopyright belongs to proceeding publishersen
description.abstractDynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.en
format.extent354228 bytes-
subjectDynamic logicen
subjectdomino logicen
subjectdiode-footed dominoen
subjectnoise toleranceen
subjectpower consumptionen
subjecttechnology scalingen
subjectsemi-dynamic logicen
titleA New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logicen
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