Please use this identifier to cite or link to this item:
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMeher, P-
dc.contributor.authorMahapatra, K K-
dc.identifier.citationInternational Conference on Computer Science and informatics, June 19-20, 2011, Bhubaneswaren
dc.descriptionCopyright belongs to proceeding publishersen
dc.description.abstractDynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.en
dc.format.extent354228 bytes-
dc.subjectDynamic logicen
dc.subjectdomino logicen
dc.subjectdiode-footed dominoen
dc.subjectnoise toleranceen
dc.subjectpower consumptionen
dc.subjecttechnology scalingen
dc.subjectsemi-dynamic logicen
dc.titleA New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logicen
Appears in Collections:Conference Papers

Files in This Item:
File Description SizeFormat 
PreetisudhaMeher.pdf310.09 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.