Please use this identifier to cite or link to this item:
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPanda, A C-
dc.contributor.authorSa, Pankaj K-
dc.contributor.authorMajhi, B-
dc.identifier.citationInternational Conference on Communication, Computing and Security(ICCCS'11), 12-14 February 2011, P 273-276en
dc.descriptionCopyright belongs to the Proceedings Publisher.en
dc.description.abstractThis paper presents a bitonic sort scheme in a shared memory mesh-connected SIMD array processor. In addition, it uses the two types of comparators of sorting networks in the mesh-connected parallel computer. This scheme uses variable multiple pivots and non-pivots. Parity strategy has been implemented to minimize the number of accesses in the mesh-connected interconnection network by introducing the concept of global and local memory. The proposed scheme is sufficiently general which is independent of hardware and interconnection network among them. From results it has been observed that by reducing the internetwork communication a performance improvement is achieved.en
dc.format.extent293970 bytes-
dc.subjectSIMD Array Processoren
dc.subjectBitonic Sorten
dc.subjectParity Strategyen
dc.titleBitonic Sort in Shared SIMD Array Processoren
Appears in Collections:Conference Papers

Files in This Item:
File Description SizeFormat 
p273-panda.pdf287.08 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.