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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1350

Title: A novel modulo (2n + 1) multiplication approach for IDEA cipher
Authors: Mukherjee, S
Sahoo, Bibhudatta
Keywords: Diminished-1 representation
IDEA cipher
Hardware Implementations
Modulo Multiplier
Partial Products
Issue Date: Nov-2010
Citation: International Journal of Programmable Device Circuits and Systems, Vol. 2, No 11, November 2010
Abstract: This paper covers the FPGA implementation of the International Data Encryption Algorithm (IDEA) using Very Large Scale Integrated Circuits Hardware Description Language (VHDL) with device as Vertex II Pro XC2VP30 using Xilinx – ISE 10.1. IDEA is very much fast and entirely based on internal group operations-XOR, modulo addition and modulo multiplication. So unlike other symmetric key block ciphers like AES or DES, there is no need for S-Boxes or P-Boxes in round operations. To use an encryption algorithm in real time applications like Cable TV, Video conferencing, the speed i.e. the data throughput rate needs to be high. The multiplication modulo (2n + 1) is the main module of this IDEA block cipher, as this module is highly computation intensive and consumes a lot of time. Due to regularity of IDEA, it has been implemented in hardware several times using different architectures. This paper mainly focuses on implementing a new algorithm and architecture for modulo (2n + 1) multiplicati...
Description: Copyright for this article belongs to Publisher
URI: http://hdl.handle.net/2080/1350
ISSN: 0974 – 973X
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