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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1295

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contributor.authorSharma, V K-
contributor.authorAgrawal, R-
contributor.authorPati, U C-
contributor.authorMahapatra, K K-
date.accessioned2010-09-27T08:57:35Z-
date.available2010-09-27T08:57:35Z-
date.issued2010-09-
identifier.citationInt’l Conf. on Computer & Communication Technology, ICCCT’10 17-19 Sept. at MNNIT Allahabaden
identifier.urihttp://hdl.handle.net/2080/1295-
descriptionCopyright belongs to the Proceeding of Publisheren
description.abstractDiscrete cosine transform (DCT) is usually used in JPEG based image transform coding. This paper presents separable 2-D discrete Hartley transform (SDHT) and its Distributed Arithmetic (DA) based hardware architecture as an alternate to DCT in transform based coding of image compression. The proposed DA architecture for 1-D DHT has very less computations as compared to existing 1-D DCT. The proposed DHT architecture implemented in FPGA indicates a significant hardware savings as compared to FPGA resources used in an efficient memory based DA approach. The additional advantage of SDHT is that its inverse transform is same as forward transform with a constant division. This is demonstrated through a Xilinx FPGA XC2VP30 device.en
format.extent191528 bytes-
format.mimetypeapplication/pdf-
language.isoen-
publisherIEEEen
subjectDistributed Arithmeticen
subjectDiscrete Hartley Transformen
subjectDiscrete Cosine Transformen
subjectJPEGen
subjectOffset Binary Codingen
title2-D Separable Discrete Hartley Transform Architecture for Efficient FPGA Resourceen
typeArticleen
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