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dc.contributor.authorSharma, V K-
dc.contributor.authorAgrawal, R-
dc.contributor.authorPati, U C-
dc.contributor.authorMahapatra, K K-
dc.identifier.citationInt’l Conf. on Computer & Communication Technology, ICCCT’10 17-19 Sept. at MNNIT Allahabaden
dc.descriptionCopyright belongs to the Proceeding of Publisheren
dc.description.abstractDiscrete cosine transform (DCT) is usually used in JPEG based image transform coding. This paper presents separable 2-D discrete Hartley transform (SDHT) and its Distributed Arithmetic (DA) based hardware architecture as an alternate to DCT in transform based coding of image compression. The proposed DA architecture for 1-D DHT has very less computations as compared to existing 1-D DCT. The proposed DHT architecture implemented in FPGA indicates a significant hardware savings as compared to FPGA resources used in an efficient memory based DA approach. The additional advantage of SDHT is that its inverse transform is same as forward transform with a constant division. This is demonstrated through a Xilinx FPGA XC2VP30 device.en
dc.format.extent191528 bytes-
dc.subjectDistributed Arithmeticen
dc.subjectDiscrete Hartley Transformen
dc.subjectDiscrete Cosine Transformen
dc.subjectOffset Binary Codingen
dc.title2-D Separable Discrete Hartley Transform Architecture for Efficient FPGA Resourceen
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