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|dc.contributor.author||Mahapatra, K K||-|
|dc.identifier.citation||International conference on Advanced Computing and Communication, May 3-4, 2010,Kanjirapally, Kerala, pp 206-210||en|
|dc.description.abstract||A Digital Signal Processor with specific instruction sets and meant for a specific application is called as Application Specific Instruction set Processor(ASIP). To design an ASIP many approaches are available. However optimization of an ASIP becomes handy if it is designed in a higher level of abstraction that is higher than Register Transfer Level (RTL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. Several stages are required to design a processor which are architecture design implementation, software development, instruction and system verification. Verification of such ASIPs at various design stages is a tedious job to do. This paper presents the architecture description of a simple DSP processor using ADL based instruction set description. The design process is more consistent after allowing maximum flexibility here. Furthermore, it enables the design process in both instruction and cycle accurate modes. The design process of a three stage pipelined FIR Filter processor is demonstrated as a case study. Further optimization can be done with respect to resources by changing the LISA code written in CoWare platform.||en|
|dc.title||Design of an Application Specific Instruction Set Processor Using LISA||en|
|Appears in Collections:||Conference Papers|
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