High-Efficiency FPGA Implementations of ASCON-128/128a: A Unified Pipelined Architecture for Authenticated Encryption in Edge Devices

Abstract

This paper presents optimized FPGA implementations of the ASCON-128 and ASCON-128a authenticated encryption algorithms across multiple Xilinx platforms. We propose both baseline and pipelined architectures that achieve an optimal balance between security, performance, and power efficiency. Our implementations demonstrate full compliance with confidentiality, integrity, and authentication (CIE) principles through rigorous functional verification. The pipelined Virtex-7 variant achieves 841 Mbps throughput with 0.540 TP/LUT efficiency, while maintaining significantly lower power consumption (0.153W-0.294W) compared to existing works. Comprehensive evaluation across seven FPGA families shows our designs achieve 1.55-4.33× better area efficiency and 1.97-3.15× lower power than state-of-the-art implementations. The Spartan-7 implementation emerges as particularly power-efficient, consuming only 0.153W at 0.56 Gbps throughput. These results establish new benchmarks for lightweight cryptographic implementations, especially suitable for resource-constrained edge devices. The paper also analyzes the area-performance tradeoffs of different architectural choices, providing valuable insights for future ASCON hardware implementations targeting IoT and embedded security applications.