Hardware Implementation of Optimized Modular Polynomial Multiplication for Post-Quantum Cryptographic Schemes

Abstract

The progress in quantum computing imposes threat to classical cryptographic systems. This led to research around the world to create new post-quantum cryptographic (PQC) algorithms. Among them, lattice-based schemes like NTRU are prominent for their security and performance. A core operation in such schemes is modular polynomial multiplication, whose efficiency critically influences overall system throughput and feasibility. Conventional polynomial multipliers often suffer from high latency and energy inefficiency, limiting hardware performance and scalability. This work presents an optimized hardware implementation for modular polynomial multiplication related to PQC. The proposed architecture maximizes parallelism through structured operand scanning and dual block computation, and it incorporates fine-grained clock gating to suppress unnecessary switching activity. Together, these features yield a design that balances area, throughput, and energy efficiency. Implementation results show that the optimized multiplier achieves 31.4% lower latency and over 30% reduction in dynamic power compared to a conventional design, with only a modest area overhead. These results demonstrate a high-performance, low-power polynomial multiplier suitable for secure PQC hardware accelerators.