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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/52

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contributor.authorMeher, P K-
contributor.authorPanda, G-
identifier.citationElectronic Letters, Vol 29, Iss 10, P 883-885en
descriptionPersonal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEen
description.abstractA recursive algorithm and a fully pipelined semisystolic CORDIC architecture for computing the 2-D discrete Hartley transform are proposed. The proposed architecture has nearly eight times the throughput rate and requires nearly (1/8)th the chip area compared with the existing CORDIC architectureen
format.extent279993 bytes-
subjectdigital arithmeticen
subjectparallel algorithmsen
subjectsystolic arraysen
titleNovel recursive algorithm and highly compact semisystolic architecture for high throughput computation of 2-D DHTen
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