Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/5010
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dc.contributor.authorYadav, Dev Narayan-
dc.contributor.authorThangkhiew, Phrangboklang Lyngton-
dc.contributor.authorLalchhandama, F-
dc.contributor.authorDatta, Kamalika-
dc.contributor.authorDrechsler, Rolf-
dc.contributor.authorSengupta, Indranil-
dc.date.accessioned2025-01-24T13:36:52Z-
dc.date.available2025-01-24T13:36:52Z-
dc.date.issued2024-12-
dc.identifier.citation33rd IEEE Asian Test Symposium (ATS 2024), Ahmedabad, Gujarat (India), 17-20 December 2024en_US
dc.identifier.urihttp://hdl.handle.net/2080/5010-
dc.descriptionCopyright belongs to the proceeding publisher.en_US
dc.description.abstractThe ability of resistive memory (ReRAM) to naturally conduct vector-matrix multiplication (VMM), the primary operation carried out in neural networks, has caught the interest of researchers. The memristor crossbar is a suitable architecture to perform VMM and additionally offers benefits like in-memory computation (IMC), low power, and high density. Memristorbased neural networks are typically trained using a mechanism where weight computations are carried out on a host machine and downloaded into the crossbar. However, due to faulty memristors in the crossbar, a cell may not be able to store the exact weight values, which may lead to inference errors. In this paper, we propose a weight-sharing method to improve the self-faulttolerance capability of memristor crossbar. In order to reduce the impact of faulty memristors, the weights are shared among different layers of memristors in a 3D crossbar. Simulation analyses show considerable improvements in the fault-tolerance capability of the crossbar.en_US
dc.subjectFault toleranceen_US
dc.subjectMemristor crossbaren_US
dc.subjectNeural networken_US
dc.subjectStuck-at-faultsen_US
dc.subjectWeight-sharingen_US
dc.titleImproving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing Approachen_US
dc.typeArticleen_US
Appears in Collections:Conference Papers

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