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Title: Low Power Sorters using Clock Gating
Authors: Preethi, K
Mohan, K.G.
Mahapatra, Kamalakanta
Kumar, Sudeendra K
Keywords: Low Power Design
Sorting architecture
Clock gating
Issue Date: Dec-2021
Citation: IEEE-iSES 2021, MNIT Jaipur, India,20-22 Dec2021
Abstract: Sorting is a very important task which is widely used in several applications like signal processing and database management. The importance of sorting has increased significantly in modern data center applications serving the applications of Cloud computing and Internet of Things. Sorting which is generally implemented in software on CPU or GPU, which takes several cycles to finish the sorting process. The further improvement in performance in sorting is possible through hardware implementation either in FPGA or ASIC. The performance improvement and reducing the power consumption are the dominant concerns. The conventional sorting techniques like Bubble sort, bitonic sort and odd-even sort are found suitable for hardware implementation in the research literature. There are several endeavors from researchers to make these sorting techniques more modular and low power, which is required to design large scale sorting for data center-based applications. In this paper, we investigate application of generic and structured low power technique like clock gating in designing the low power sorters. The bubble sort, bitonic sort and odd-even sorting techniques are redesigned to make them low power using clock gating technique. The implementation results show that, the clock gating reduces the dynamic power consumption on sorters by 47.5% without much impact on the performance. The power reduction results obtained are comparable with state-of-the-art low power sorters which are complex in design. The proposed sorters are implemented and results are presented for Saed90nm standard cell libraries.
Description: Copyright of this paper is with proceedings publisher
Appears in Collections:Conference Papers

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