Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic

Abstract

In this paper, we have proposed a new fault tolerant design technique for majority voter that is used in selection of final output for fault-tolerant methods like N-tuple modular redundancy (NMR) and N-tuple interwoven redundancy (NIR). The common assumption that majority voters are robust and hence does not affect the final reliability of a system, is false for most of the practical applications. We have used redundancy at transistor level combined with redundancy at gate level to design a defect tolerant majority voter that provides notable improvement in reliability over conventional triple modular redundancy technique using traditional non-reliable voters and other existing methods