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dc.contributor.authorChowdhury, Joy-
dc.contributor.authorDeyasi, Arpan-
dc.contributor.authorSarkar, Angsuman-
dc.contributor.authorMahapatra, Kamalakanta-
dc.identifier.citation5th IEEE International Symposium on Smart Electronic Systems ( IEEE-iSES 2019 ), Rourkela, India, 16-18 December 2019.en_US
dc.descriptionCopyright of this document belongs to proceedings publisher.en_US
dc.description.abstractThreshold voltage (with and without body bias) for heterostructure pMOSFET is analytically explored as a function of applied bias for Si-SixGe1-x material system in presence of band-to-band tunneling. Threshold voltage for given device structure is calculated in the light of body effect for different structural parameters, and mole fraction of Ge is chosen as 0.28 for that operating point where 2DEG is yet to be formed, and thus making it apposite for estimating subthreshold conduction. Using this optimum structure, BTBT effect is incorporated to quantity the variation of threshold voltage over a range of source-to-gate voltages (VSG). The results accord with available experimental data for very low and higher values of source-to-drain voltage (VSD). Result is also computed in absence of tunneling effect, and drastic variation is observed which speaks in favor of our proposed model of subthreshold conduction which can be further extended for modeling of sub-threshold drain current characteristics of HFETs.en_US
dc.subjectTunneling windowen_US
dc.subjectHeterostructure FETen_US
dc.subjectHeterostructure FETen_US
dc.subjectThreshold Voltageen_US
dc.subjectStructural parametersen_US
dc.subjectHigh-K dielectricen_US
dc.titleNovel Threshold Voltage Model incorporating Band-To-Band Tunneling in Heterostructure p-MOSFETen_US
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