Please use this identifier to cite or link to this item:
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPyne, Sumanta-
dc.identifier.citation31st International Conference on VLSI Design & 17th International Conference on Embedded Systems, Pune, India, 8 - 10 January, 2018en_US
dc.descriptionCopyright of this document belongs to proceedings publisher.en_US
dc.description.abstractThe present work introduces two compilation techniques for reduction of in-rush current in processors with power gating (PG) facility. These are done by rescheduling the PG instructions responsible in turning on multiple components from sleep to active mode at overlapped time intervals. The first method eliminates overlapped wake-up of the components resulting lesser in-rush current at the cost of performance degradation due to increase in program size. The second method allows overlapped wake-up as long as the resultant in-rush current is tolerable by the system with lesser increase in delay and program size. Algorithms are designed to automate these methods. The efficacy of the proposed methods are evaluated on MiBench and MediaBench benchmark programs. The original program with PG and their translated versions are executed on gem5 which simulates ARM Cortex-M4F processor enhanced with PG. McPAT is used to find the values of power consumed and in-rush current. The first and second methods reduce in-rush current by an average of 54% and 35%, respectively with corresponding average performance loss of 21% and 9%.en_US
dc.subjectPower gating (PG) facilityen_US
dc.subjectIn-rush currenten_US
dc.titleRescheduling of Power Gating instructions for reduction of In-rush currenten_US
Appears in Collections:Conference Papers

Files in This Item:
File Description SizeFormat 
2018_VLSID_SPyne_Rescheduling.pdfConference Paper353.01 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.