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Title: A Modified RO-PUF with Improved Security Metrics on FPGA
Authors: Satheesh, N
Mahapatra, A
Sudeendra Kumar, K
Sahoo, S
Mahapatra, K K
Keywords: Physical Unclonable Function
Hardware Security
Issue Date: Dec-2016
Publisher: IEEE
Citation: IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), ABV-IITM, Gwalior, India, 19-21 December 2016
Abstract: Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO’s to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.
Description: Copyright belongs to the proceeding publisher
Appears in Collections:Conference Papers

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