A Power Improvement Technique for a Differential LNA

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1933

Full metadata record

DC Field	Value	Language
dc.contributor.author	Swamy, M N	-
dc.contributor.author	Acharya, D P	-
dc.date.accessioned	2013-04-22T09:57:24Z	-
dc.date.available	2013-04-22T09:57:24Z	-
dc.date.issued	2013-04	-
dc.identifier.citation	2nd Students' Conference on Engineering and Systems (SCES 2013) April 12-14, 2013,MNNIT Allahabad	en
dc.identifier.uri	http://hdl.handle.net/2080/1933	-
dc.description	Copyright belongs to proceeding publisher	en
dc.description.abstract	This work presents the design of an inductively source degenerated CMOS Differential Low Noise Amplifier (LNA) operating at 2 GHz. LNA is designed using UMC 0.18 μm technology and simulated in Cadence Spectre_RF tool to validate its performance. Power constrained methodology is used for the design of CMOS Differential Low Noise Amplifier. At 1.8V supply voltage, the designed LNA consumed 9mA current. The amplifier....	en
dc.format.extent	244992 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.subject	Low Noise Amplifier (LNA)	en
dc.subject	CMOS	en
dc.subject	noise figure (NF)	en
dc.subject	Power	en
dc.title	A Power Improvement Technique for a Differential LNA	en
dc.type	Article	en
Appears in Collections:	Conference Papers

Files in This Item:

File	Description	Size	Format
finalpaper_paper284.pdf		239.25 kB	Adobe PDF	View/Open