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Title: An Ultra Low Power Encoder for 5 Bit Flash ADC
Authors: Lavania, Y
Varghese, G T
Mahapatra, K K
Keywords: Analog to digital converter
Flash ADC
Dynamic CMOS logic
Issue Date: Jan-2013
Citation: IEEE EDS & SKP ICEVENT 2013,International conference on Emerging Trends in VLSI, Embedded Systems, Nano Electronics and Telecommunication System, SKP Engg. College, Tiruvannamalai, 07-Jan-2013 to 09-Jan-2013
Abstract: This investigation suggests a low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital convert-er. One of the demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this paper converts the thermometer code into binary code without any intermediate stage. To decrease the power consumption of the encoder, the implementation is done using dynamic CMOS logic. The proposed encoder is designed using 90 nm technology at 1.2 V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 4GHz and the average power dissipation of the encoder is 1.833 μW.
Description: Copyright belongs to proceeding publisher
Appears in Collections:Conference Papers

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